1. Technical Field of the Invention
The present invention generally relates to semiconductor memory circuits and, in particular, to a dynamic random access memory (DRAM) circuit having a testing system and method to determine the sensitivity of a sense amplifier.
2. Description of Related Art
It is well known that a computer system requires memory to store data regardless of whether the computer system is a large machine or a microcomputer. The computer system can use a type of memory known as semiconductor memory to store data in either non-volatile memory or volatile memory.
Semiconductor memory that loses data upon removal of a power supply is volatile memory and can be further classified as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). Static Random Access Memory includes a flip-flop and multiple transistors that maintain a bit of data so long as power is present. Dynamic Random Access Memory, on the other hand, includes a memory cell that has a transistor and storage capacitor to maintain a charge representing a bit of data for a short period of time unless the memory cell is periodically refreshed.
The DRAM also includes a sense amplifier for sensing a voltage differential that appears between a first bit line and second bit line during a read operation of the memory cell. The sense amplifier determines a binary value of the data represented by the charge maintained in the memory cell by comparing a voltage level corresponding to the charge of the memory cell that is transferred to the first bit line to that of a precharge voltage (e.g., Vdd/2) present on the second bit line. However, since the voltage level within the storage capacitor of the memory cell decays towards ground, the detection of a "high" binary value by the sense amplifier becomes more difficult as the voltage level within the storage capacitor decays closer to the precharge voltage.
In addressing the decaying problem of the storage capacitor, DRAM circuit currently uses a dummy cell to aid the sense amplifier in detecting the "high" binary values by setting a dummy voltage within the dummy cell to a level below the conventional precharged voltage of Vdd/2 and comparing the dummy voltage instead of the conventional precharge voltage to the voltage level of the memory cell. The utilization of the dummy voltage set below the traditional precharge voltage increases the margin for detecting the "high" binary value of the memory cell, at the expense of a corresponding decrease in the margin for detecting a "low" binary value of the memory cell.
Unfortunately, the current use of the dummy cell to increase the margin for detecting the "high" binary value within the memory cell fails to address a problem where the sense amplifier itself may be defective. For instance, the sense amplifier may not have sufficient sensitivity to correctly identify the binary value or voltage level of the memory cell regardless of the setting of the margins. Therefore, there is a need for a dynamic random access memory (DRAM) circuit incorporating a testing system and method used to determine the sensitivity of a sense amplifier.